Latest Technology Behind AMD APU "Trinity"

 

APU (Accellerated Processing Unit) Trinity

AMD Trinity APU processor comprises x86/x64 computing unit (CPU) and graphics computing unit (GPU). In the intact condition, Trinity APU will have 4 cores processor with 2 units of L2-cache. While the unit is GPU graphics card AMD HD 7000 series.

AMD uses the fabrication process as Llano APU for Trinity APU that is 32 nm. An increase in the number of transistors on Trinity APU Llano APU compared, from 1.178 billion to 1.303 billion transistors. An increasing number of transistors and use the same fabrication process has broad measure Trinity APU die increased to 246 mm2 from 228 ​​mm2 to previous Llano APU.

Prosesor

By looking at the AMD APU processor die picture above, please see the difference between Llano and Trinity, especially in the CPU unit. Trinity APU now uses the Piledriver architecture, the successor architecture on an AMD Bulldozer FX series. As the successor to Bulldozer, Piledriver CPU unit is still adheres to the same scheme is a module for two integer cores and one core FPU (floating point unit). The maximum number of modules in the Trinity APU is 2 pieces with the size of the L2 cache 2MB per module.

Here are some improvement compared Piledriver Bulldozer architecture. AMD adds some new instructions such as AVX, AVX 1.1, FMA3, AES, and F16C. Architecture Pildriver claimed to have 10-15% better performance than Bulldozer and 26% better than Llano APU CPU unit due to an increase in the IPC (Instructions Per Clock) processor.

In addition to the CPU unit with the latest architecture, Trinity APU is now also using new types Unified Northbridge Northbridge (UNB). To communicate with other devices, UNB no longer uses HyperTransport but using PCIe lanes. Fixed memory controller supports dual channel DDR3 memory with a maximum speed of 1866 MHz. Memory controller now supports DDR3 memory voltage 1.25 V.

For PCIe controller, APU Trinity is not much different from the Llano APU is still using the second-generation PCI Express PCIe lanes with 24 pieces of track which can be divided for multi-GPU feature to accommodate the communication lines or other components.